The accelerating arms race between IT hardware manufacturers to develop more energy efficient systems stepped up a gear at the International Solid State Circuits Conference (ISSCC) in San Francisco this week where both IBM and AMD revealed plans for new low power chips.
IBM was first out the blocks, detailing how its upcoming Power6 chip would deliver double the performance of its Power5+ chip while using the same amount of power.
According to reports the chip will have a new "nap" mode that cuts power consumption by up to 35 percent when a server's operating system is idle and will also provide new power management capabilities that will cut processor frequency and voltage when required.
The company said it would also allow users to "cap" maximum power usage, making it far easier for them to manage the power demands of a given server. Currently, estimating how much power a server will require is a tricky task with many manufacturers only providing details on maximum power requirements. But as chips may rarely approach this maximum firms are often left having to arrange to deliver far more power into a datacentre than they actually need. Capping the amount of power any chip can use would, in theory, make it far easier to optimise the energy efficiency of the datacentre.
Meanwhile, chip manufacturer AMD confirmed that the four cores in its imminent quad-core Opteron processor, codenamed Barcelona, will be able to operate at different speeds simultaneously, potentially slashing energy demands.
The company said the new chip would use an updated version of its PowerNow technology to reduce overall power requirements by ensuring that cores can crank down their speed based on their workloads.
According to reports, this ability for the cores to operate independently means AMD is confident it can cut power consumption by an average of around 10 watts compared to current AMD dual-core processors where the two cores have to move together.
Separately, AMD also demonstrated a new memory controller that allows the read/write memory to power down when not in use, reducing power consumption by 80 percent on previous models.
The company said that Barcelona would have a thermal envelope of 68, 95 or 120 watts depending on the model.
The on-going interest in energy efficiency from leading chip manufacturers at the ISSCC event further highlights the extent to which a desire to improve both energy efficiency and performance has now fully replaced the sole focus on enhancing performance that previously dominated computer chip design.
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